Computer Engineering seminars

Srini Devadas examines how hardware and cryptography can strengthen each other. Hardware can protect keys, monitor attacks in real time and reduce the trusted computing base, while hardware vulnerabilities can undermine software security. The talk presents research on accelerating cryptographic computation and using those capabilities to design more efficient protocols. It also asks how cryptography and new security definitions can guide the construction of secure hardware. Devadas is MIT's Webster Professor of Electrical Engineering and Computer Science. Hybrid: MIT Stata Center, Room 32-G449 (Kiva), 32 Vassar Street, Cambridge, MA 02139; online via Zoom. Thursday 24 September 2026, talk at 19:00 EDT (UTC−4); in-person refreshments begin at 18:30. This public event is organized by the Boston Chapter of the IEEE Computer Society and GBC/ACM. Register through the organizer-linked Zoom form for either mode and indicate online or in-person attendance. For physical access, use the Stata Center entrance nearest Main Street, then the fourth-floor elevators.

Paritosh Ramanan presents algorithm–hardware co-design for reliable linear algebra and optimization on resistive-memory in-memory computing systems. The distributed MELISO simulation framework supports multiple hardware models, while multilevel error correction makes noisy, low-energy devices useful for matrix-vector multiplication. Simulations report energy improvements of up to five orders of magnitude and latency reductions of up to two for high-dimensional linear algebra. A distributed primal-dual hybrid gradient solver for linear programs combines convergence analysis under device noise with simulated gains of up to two orders in latency and three in energy over GPU baselines on medium-scale problems. Preliminary randomized Kaczmarz results use online signal-to-noise estimates to select rows, comparing this strategy with offline alternatives. The talk closes with open problems in in-memory computation.

Engineered pattern-recognition systems strive for short time-to-solution and low energy-to-solution characteristics. This represents one of the main driving forces behind the development of neuromorphic devices. For both them and their biological archetypes, this corresponds to using as few spikes as early as possible. The concept of few and early spikes is used as the founding principle in the time-to-first-spike coding scheme. Within this framework, we have developed a spike-timing-based learning algorithm, which we used to train neuronal networks on the mixed-signal neuromorphic platform BrainScaleS-2. We derive, from first principles, error-backpropagation-based learning in networks of leaky integrate-and-fire (LIF) neurons relying only on spike times, for specific configurations of neuronal and synaptic time constants. We explicitly examine applicability to neuromorphic substrates by studying the effects of reduced weight precision and range, as well as of parameter noise. We demonstrate the feasibility of our approach on continuous and discrete data spaces, both in software simulations and on BrainScaleS-2. This narrows the gap between previous models of first-spike-time learning and biological neuronal dynamics and paves the way for fast and energy-efficient neuromorphic applications.

The potential of machine learning and deep learning to advance artificial intelligence is driving a quest to build dedicated computers, such as neuromorphic hardware that emulate the biological processes of the brain. While the hardware technologies already exist, their application to real-world tasks is hindered by the lack of suitable programming methods. Advances at the interface of neural computation and machine learning showed that key aspects of deep learning models and tools can be transferred to biologically plausible neural circuits. Building on these advances, I will show that differentiable programming can address many challenges of programming spiking neural networks for solving real-world tasks, and help devise novel continual and local learning algorithms. In turn, these new algorithms pave the road towards systematically synthesizing machine intelligence in neuromorphic hardware without detailed knowledge of the hardware circuits.