Computer Engineering

Srini Devadas examines how hardware and cryptography can strengthen each other. Hardware can protect keys, monitor attacks in real time and reduce the trusted computing base, while hardware vulnerabilities can undermine software security. The talk presents research on accelerating cryptographic computation and using those capabilities to design more efficient protocols. It also asks how cryptography and new security definitions can guide the construction of secure hardware. Devadas is MIT's Webster Professor of Electrical Engineering and Computer Science. Hybrid: MIT Stata Center, Room 32-G449 (Kiva), 32 Vassar Street, Cambridge, MA 02139; online via Zoom. Thursday 24 September 2026, talk at 19:00 EDT (UTC−4); in-person refreshments begin at 18:30. This public event is organized by the Boston Chapter of the IEEE Computer Society and GBC/ACM. Register through the organizer-linked Zoom form for either mode and indicate online or in-person attendance. For physical access, use the Stata Center entrance nearest Main Street, then the fourth-floor elevators.

Over the past decade our community has made substantial progress in the construction of anatomically detailed network models of the cortical tissue. Thanks to advances in computer hardware and simulation technology, researchers can now routinely work with these models at the natural density of neurons and synapses. Moreover, the availability of cloud services means that such investigations can be carried out without having to install either the model or the simulation software. A recent workshop analyzed the impact of a specific model of the cortical microcircuit, published ten years ago . The model has been reused in multiple contexts: for reproduction studies, validation of mean-field approaches, exploration of methods of model sharing, and as a building block for larger models. Although the model was less successful in inspiring further neuroscientific studies than the authors of the original work had hoped, it became a de facto benchmark for neuromorphic computing systems. It sparked a constructive race for ever shorter simulation times and lower energy consumption. The quantitative comparison of different platforms reveals qualitative differences between conventional and neuromorphic hardware and limits of speed-up. The structure of the model is based on light microscopy because these were the data available at the time. Guided by simulation results and physiological evidence, the original publication hypothesized a preference of excitatory neurons for inhibitory targets. Modern electron microscopy data of cortical volumes combined with AI based reconstruction techniques is capable of resolving individual synaptic connections. This advances the concept of digital twins of the cortical network to a new level of precision, and has already enabled us to confirm the assumption of target type specifity underlying earlier models. Maybe with the progress sketched here, our community is at a transition point where it becomes easier to cooperatively and incrementally work on models with a larger explanatory scope. Presented in the van Vreeswijk Theoretical Neuroscience Seminar series (formerly WWTNS) on 2025-12-10. Recording duration: 00:39:15.

UK Research and Innovation is funding speculative, high-risk projects that could deliver a step change in the sustainability of future AI systems. Proposals may address energy-efficient algorithms, resource-constrained AI, hardware-software co-design, repairable hardware, and other technology-led advances across the AI stack.

Srini Devadas examines how hardware and cryptography can strengthen each other. Hardware can protect keys, monitor attacks in real time and reduce the trusted computing base, while hardware vulnerabilities can undermine software security. The talk presents research on accelerating cryptographic computation and using those capabilities to design more efficient protocols. It also asks how cryptography and new security definitions can guide the construction of secure hardware. Devadas is MIT's Webster Professor of Electrical Engineering and Computer Science. Hybrid: MIT Stata Center, Room 32-G449 (Kiva), 32 Vassar Street, Cambridge, MA 02139; online via Zoom. Thursday 24 September 2026, talk at 19:00 EDT (UTC−4); in-person refreshments begin at 18:30. This public event is organized by the Boston Chapter of the IEEE Computer Society and GBC/ACM. Register through the organizer-linked Zoom form for either mode and indicate online or in-person attendance. For physical access, use the Stata Center entrance nearest Main Street, then the fourth-floor elevators.